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4 mhz, 7 nv/hz, low offset and drift, high precision amplifiers data sheet ada4077 - 1 / ada4077 - 2 / ada4077 - 4 rev. d document feedback information furnished by analog devices is believed to be accurate and reliabl e. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implicatio n or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2016 analog devices, inc. all rights reserved. technical support www.analog.com features o ffset voltage and offset voltage drift b g rade : 25 v and 0.25 v/ c at v sy = 5 v a grade maximum offset at 25c and maximum drift from ?40c to +125c soic: 50 v and 0.55 v/c single/dual and 0.75 v/c quad msop: 90 v and 1.2 v/c dual and 120 v and 1.2 v/c single tssop: 120 v and 1.2 v/c quad msl1 rated low input bias current: 1 na maximum at t a = 25c low voltage noise density : 6.9 nv/hz typical at f = 100 0 hz cmrr, psrr, and a v > 120 db minimum low supply current: 400 a per amplifier typical wide gain b andwidth product : 3.9 mhz at 5 v dual - sup ply operation: 2. 5 v to 1 5 v unity gain stable no phase reversal applications process control front - end amplifiers wireless base station control circuits optical network control circuits instrumentation sensors and controls : t hermocouples , rtds , s train bridges , and s hunt current measurements precision filters general description the single ada4077 - 1 , dual ada4077 - 2 , and quad ada4077 - 4 amplifiers feature extremely low offset voltage and drift, and low input bias current, noise, and power consumption . outputs are stable with capacitive loads of more than 1000 pf with no external compensation. applications for t his amplifier include sensor signal conditioning (such as thermocouples, rtds, strain gauges), process control front - end amplifiers, and precision diode power measurement in optical and wireless transmission systems. the ada4077 - 1 , ada4077 - 2 , and ada4077 - 4 are useful in l ine powered and portable instrumentation, precision filters, and voltage or current measurement and level setting. unlike amplifiers by some competitors, the ada4077 - 1 / ada4077 - 2 / ada4077 - 4 have an msl1 rating that is compliant with the most stringent of assembly processes, and they are specified over the extended industrial temperature range from ?40c to +125c for the most demanding operating environments. pin c onnection diagrams figure 1. ada4077 - 1 , 8- lead soic ( and 8 - lead msop ) figure 2. ada4077 - 2, 8 - lead msop ( and 8- lead soic ) figure 3. ada4077 - 4 , 14 - lead tssop ( and 14 - lead soic ) the ada4077 - 1 and ada4077 - 2 are available in an 8 - lead soic package, including the b g rade, and in an 8 - lead msop (a g rade only). the ada4077 - 4 is offered in a 14 - lead tssop and a 14 - lead soic package. figure 4 . offset voltage distribution table 1 . evolution of precision devices by generation op amp first second third fourth fifth sixth single op07 op77 op177 op1177 ad8677 ada4077 - 1 dual op2177 ada4077 - 2 quad op4177 ada4077 - 4 nc 1 ?in 2 +in 3 v? 4 nc 8 v+ 7 out 6 nc 5 nc = no connec t . not internal l y connected. ADA4077-1 t o p view (not to scale) 10238-101 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t op view (not to scale) 10238-001 ada4077-4 1 2 3 4 5 6 7 ?in a +in a v+ out b ?in b +in b out a 14 13 12 1 1 10 9 8 ?in d +in d v? out c ?in c +in c out d t op view (not to scale) 10238-202 v os (v) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 0 20 40 60 80 100 120 140 160 180 200 10238-103 v sy = 5v soic
ADA4077-1/ada4077-2/ada4077-4 data sheet rev. d | page 2 of 25 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 pin connection diagrams ............................................................... 1 revisi on history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics, 5 v .................................................. 3 electrical characteristics, 15 v ................................................ 5 absolute maximum ratings ....................................................... 7 thermal resistance ...................................................................... 7 esd caution ...................................................................................7 pin configurations and function descriptions ............................8 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 21 applications information .............................................................. 22 output phase reversal ............................................................... 22 low power linearized rtd ...................................................... 22 prop er board layout .................................................................. 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 25 revision history 10 /2016r ev. c to rev. d c hanges to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 5 changes to figure 19 ...................................................................... 12 changes to figure 23 and figure 26............................................. 13 changes to figure 29 , figure 30 , figure 32 , and figure 33 ...... 14 6/ 2015 rev. b to rev. c change to figure 63 ....................................................................... 18 1/ 2014 rev. a to rev. b added ada 4077 -1 ............................................................. universal changes to features section ............................................................ 1 added figure 1 ; renumbered sequentially .................................. 1 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 4 added figure 5 , f igure 6, and table 6; renumbered sequentially ....................................................................................... 7 c hanges to figure 17 , figure 20 , and figure 21 ......................... 11 changes to figure 65 ...................................................................... 19 added figure 67 and figure 68 .................................................... 19 changes to output phase reversal section and figure 70 ....... 21 changes to ordering guide .......................................................... 24 10/ 2013 rev. 0 to rev. a added ada 4077 -4 ............................................................. universal changes to features, general description, and figure 1 ............. 1 deleted figure 2 ; renumbered sequentially ................................. 1 added figure 2 .................................................................................. 1 changes to table 2 ............................................................................. 3 changes to table 3 ............................................................................. 4 changes to table 4 ............................................................................. 6 added figure 6 , figure 7, and table 7 ; renumbered sequentially ........................................................................................ 8 changes to typical performance characteristics section ........... 9 changes to figure 65 ...................................................................... 20 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 23 10 / 2012 revision 0: initial version
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 3 of 25 specifications electrical character istics , 5 v v s y = 5.0 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 2 . parameter symbol test conditions/comme nt s min typ max unit input characteristics offset voltage v os ada4077 - 1 / ada4077 -2 b grade, soic 10 25 v ?40c < t a < +125c 65 v a grade, soic 15 50 v ?40c < t a < +125c 105 v a grade, msop 50 90 v ?40c < t a < +125c 220 v ada4077 -4 a grade, soic 15 50 v ?40c < t a < +125c 105 v a grade, tssop 15 120 v ?40c < t a < +125c 220 v offset voltage drift ?v os /?t ?40c < t a < +125c ada4077 - 1 / ada4077 -2 b grade, soic 0.1 0.25 v/c a grade, soic 0.25 0.55 v/c a grade, msop 0.5 1.2 v/c ada4077 - 4 a grade, soic 0.4 0.75 v/c a grade, tssop 0.5 1.2 v/c input bias current i b ?1 ?0.4 +1 na ?40c < t a < +125c ?1.5 +1.5 na input offset current i os ?0.5 +0.1 +0.5 na ?40c < t a < +125c ?1 +1 na input voltage range ?3.8 +3 v common - mode rejection ratio cmrr v cm = ?3.8 v to +3 v 122 140 db v cm = ?3.8 v to +3 v, ?40c < t a < +85c 120 db v cm = ?3.8 v to +2.8 v, 85c < t a < 125c 120 db large signal voltage gain av r l = 2 k, v o = ? 3.0 v to +3.0 v 121 130 db ?40c < t a < +125c 120 db input capacitance c incm common mode 5 pf input resistance r in common mode 70 g output characteristics output voltage high v oh i l = 1 ma 3.8 v ?40c < t a < +125c 3.7 v output voltage low v ol i l = 1 ma ? 3.8 v ?40c < t a < +125c ? 3.7 v output current i out v dropout < 1.6 v 10 ma short - circuit current i sc t a = 25 c 22 ma closed - loop output impedance z out f = 1 khz, a v = +1 0.05 power supply power supply rejection ratio psrr v s = 2.5 v to 18 v 123 128 db ?40c < t a < +125c 120 db supply current per amplifier i sy v o = 0 v 400 450 a ?40c < t a < +125c 650 a
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 4 of 25 parameter symbol test conditions/comme nt s min typ max unit dynamic performance slew rate sr r l = 2 k 1.2 v/s settling time to 0.1% t s v in = 1 v step, r l = 2 k , a v = ?1 3 s gain bandwidth product gbp v in = 10 mv p - p, r l = 2 k, a v = +100 3.9 mhz unity - gain crossover ugc v in = 10 mv p - p, r l = 2 k, a v = + 1 3.9 mhz ?3 db closed - loop bandwidth ?3 db a v = +1, v in = 10 mv p - p, r l = 2 k 5.9 mhz phase margin m v in = 10 mv p - p, r l = 2 k, a v = +1 55 degrees total harmonic distortion plus noise thd + n v in = 1 v rms, a v = +1, r l = 2 k, f = 1 khz 0.004 % noise performance voltage noise e n p -p 0.1 hz to 10 hz 0.25 v p -p voltage noise density e n f = 1 hz 13 nv/hz f = 100 hz 7 nv/hz f = 1000 hz 6.9 nv/hz current noise density i n f = 1 khz 0.2 pa/hz multiple amplifiers channel separation c s f = 1 khz, r l = 10 k ?125 db
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 5 of 25 electrical character istics , 15 v v s y = 15 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 3 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os ada4077 - 1 / ada4077 -2 b grade, soic 10 35 v ?40c < t a < +125c 65 v a grade, soic 15 50 v ?40c < t a < +125c 105 v a grade, msop 50 90 v ?40c < t a < +125c 220 v ada4077 -4 a grade, soic 15 50 v ?40c < t a < +125c 105 v a grade, tssop 15 120 v ?40c < t a < +125c 220 v offset voltage drift ?v os /?t ada4077 - 1 / ada4077 - 2 b grade, soic ?40c < t a < +125c 0.1 0.25 v/c a grade, soic ?40c < t a < +125c 0.25 0.55 v/c a grade, msop ?40c < t a < +125c 0.5 1.2 v/c ada4077 -4 a grade, soic ?40c < t a < +125c 0.4 0.75 v/c a grade, tssop ?40c < t a < +125c 0.5 1.2 v/c input bias current i b ?1 ?0.4 +1 na ?40c < t a < +125c ?1.5 +1.5 na input offset current i os ?0.5 +0.1 +0.5 na ?40c < t a < +125c ?1 +1 na input voltage range ?13.8 +13 v common - mode rejection ratio cmrr v cm = ?13.8 v to +13 v 132 150 db ?40c < t a < +125c 130 db large signal voltage gain av ada4077 - 1 / ada4077 -2 (soic, msop) r l = 2 k, v o = ?13.0 v to +13.0 v 125 130 db ?40c < t a < +125c 120 db ada4077 -4 (soic, tssop) r l = 2 k, v o = ?13.0 v to +13.0 v 122 130 db ?40c < t a < +125c 120 db input capacitance c indm differential mode 3 pf c incm common mode 5 pf input resistance r in common mode 70 g output characteristics output voltage high v oh i l = 1 ma 13.8 v ?40c < t a < +125c 13.7 v output voltage low v ol i l = 1 ma ?13.8 v ?40c < t a < +125c ?13.7 v output current i out v dropout < 1.2 v 10 ma short - circuit current i sc t a = 25 c 22 ma closed - loop output impedance z out f = 1 khz, a v = +1 0.05
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 6 of 25 parameter symbol test conditions/comments min typ max unit power supply power supply rejection ratio psrr v s = 2.5 v to 18 v 123 128 db ?40c < t a < +125c 120 db supply current per amplifier i sy v o = 0 v 400 500 a ?40c < t a < +125c 650 a dynamic performance slew rate sr r l = 2 k 1.2 v/s settling time to 0.01% t s v in = 10 v p - p, r l = 2 k, a v = ?1 16 s settling time to 0.1% t s v in = 10 v p - p, r l = 2 k , a v = ?1 10 s gain bandwidth product gbp v in = 10 mv p - p, r l = 2 k, a v = +100 3.6 mhz unity - gain crossover ugc v in = 10 mv p - p, r l = 2 k, a v = + 1 3.9 mhz ?3 db closed - loop bandwidth ?3 db a v = + 1, v in = 10 mv p - p, r l = 2 k 5.5 mhz phase margin m v in = 10 mv p - p, r l = 2 k, a v = +1 58 degrees total harmonic distortion plus noise thd + n v in = 1 v rms, a v = +1, r l = 2 k, f = 1 khz 0.004 % noise performance voltage noise e n p -p 0.1 hz to 10 hz 0.25 v p -p voltage noise density e n f = 1 hz 13 nv/hz f = 100 hz 7 nv/hz f = 1000 hz 6.9 nv/hz current noise density i n f = 1 khz 0.2 pa/hz multiple amplifiers channel separation c s f = 1 khz, r l = 10 k ?125 db
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 7 of 25 absolute maximum rat ings table 4 . parameter rating supply voltage 36 v input voltage v sy input current 1 10 ma differential input voltage v sy output short - circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature, soldering (10 sec) 300c esd human body model (hbm) 2 6 kv field induced charge device model (ficdm) 3 1.25 kv 1 the input pins have clamp diodes to the power supply pins and to each other. limit the input current to 10 ma or less whenever input signals exceed the power supply rail by 0.3 v. 2 esda/jedec js - 001- 2011 applicable standard . 3 jesd22 - c101 (esd ficdm standard of jedec) applicable standard. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specif ied for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc unit 8 - lead msop 190 44 c/w 8 - lead soic 158 43 c/w 14 - lead tssop 240 43 c/w 14 - lead soic 115 36 c/w esd caution
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 8 of 25 pin configurations a nd function descript ions figure 5. ada4077 - 1 pin configuration, 8 - lead msop (rm - 8) figure 6. ada4077 - 1 pin configuration, 8 - lead soic (r - 8) table 6 . ada4077 - 1 pin function descriptio ns, 8 - lead msop and 8 - lead soic pin no. mnemonic description 1 , 5, 8 nc no connect. not internally c onnected. 2 ?in inverting input . 3 +in non inverting input . 4 v? negative supply voltage . 6 out output . 7 v+ positive supply voltage. nc ?in +in v? nc v+ out nc nc = no connec t . not internal l y connected. ADA4077-1 t op view (not to scale) 10238-205 1 2 3 4 8 7 6 5 nc 1 ?in 2 +in 3 v? 4 nc 8 v+ 7 out 6 nc 5 nc = no connec t . not internal l y connected. ADA4077-1 t op view (not to scale) 10238-105
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 9 of 25 figure 7. ada4077 - 2 pin configuration, 8 - lead msop figure 8. ada4077 - 2 pin configuration, 8 - lead soic table 7 . ada4077 - 2 pin function descriptions , 8 - lead msop and 8 - lead soic pin o. mnemonic description 1 out a output channel a . 2 ?in a inverting input channel a . 3 +in a noninverting input channel a . 4 v? negative supply voltage . 5 +in b noninverting input channel b . 6 ?in b inverting input channel b . 7 out b output channel b . 8 v+ positive supply voltage . out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t o p view (not to scale) 10238-004 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t op view (not to scale) 10238-005
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 10 of 25 figure 9. ada4077 - 4 pin configuration, 14 - lead tssop figure 10 . ada4077 - 4 pin configuration, 14 - lead soic table 8 . ada4077 - 4 pin function descriptions, 14 - lead tssop and 14 - lead soic pin no. mnemonic description 1 out a output channel a . 2 ?in a negative input channel a . 3 +in a positive input channel a . 4 v+ positive supply voltage . 5 +in b positive input channel b . 6 ?in b negative input channel b . 7 out b output channel b . 8 out c output channel c . 9 ?in c negative input channel c . 10 +in c positive input channel c . 11 v? negative supply voltage . 12 +in d positive input channel d . 13 ?in d negative input channel d . 14 out d output channel d . ada4077-4 1 2 3 4 5 6 7 ?in a +in a v+ out b ?in b +in b out a 14 13 12 1 1 10 9 8 ?in d +in d v? out c ?in c +in c out d t op view (not to scale) 10238-206 out a 1 ?in a 2 +in a 3 v+ 4 out d 14 ?in d 13 +in d 12 v? 1 1 +in b 5 +in c 10 ?in b 6 ?in c 9 out b 7 out c 8 ada4077-4 t o p view (not to scale) 10238-207
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 11 of 25 typical performance characteristics figure 11 . ada4077 - 2 offset voltage (v os ) distribution , v sy = 5 v figure 12 . offset voltage (v os ) distribution , v sy = 5 v figure 13 . offset voltage (v os ) vs. temperature , v sy = 5 v figure 14 . ada4077 - 2 offset voltage (v os ) distribution , v sy = 15 v figure 15 . offset voltage (v os ) distribution , v sy = 15 v figure 16 . offset voltage (v os ) vs. temperature , v sy = 15 v 0 20 40 v os (v) 60 80 100 120 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 10238-006 v sy = 5v msop v os (v) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 0 20 40 60 80 100 120 140 160 180 200 10238-144 v sy = 5v soic ?10 ?5 0 5 10 15 20 ?50 ?25 0 25 50 75 100 125 v os (v) temper a ture (c) 10238-210 v sy = 5v 0 20 40 60 80 100 120 140 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 more v os (v) number of amplifiers 10238-003 v sy = 15v msop v os (v) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 0 20 40 60 80 100 120 140 160 180 200 10238-009 v sy = 15v soic ?15 ?10 ?5 0 5 10 15 ?50 ?25 0 25 50 75 100 125 v os (v) temper a ture (c) 10238-213 v sy = 15v
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 12 of 25 figure 17 . tcv os (tssop and msop, a grade ) figure 18 . offset voltage (v os ) vs. voltage supplies (v sy ) figure 19 . offset voltage (v os ) vs. common - mode voltage (v cm ), v sy = 15 v figure 20 . tcv os ( soic, a grade) figure 21 . tcv os ( soic, b grade) figure 22 . supply current per amplifier ( i sy ) vs. power supply v oltage (v sy ) tcv os (v/c) number of amplifiers 10238-130 0 5 10 15 20 25 30 35 40 45 50 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 v sy = 15 v , 5v tsso p and mso p , a grade 10 ?10 0 35 v os (v) v sy (v) 10238-134 ?5 0 5 5 10 15 20 25 30 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ?15 ?13 ? 1 1 ?9 ?7 ?5 ?3 ?1 1 3 5 7 9 1 1 13 15 v os (v) v cm (v) average average +3 average C3 10238-419 v s = 15v C15v v cm +15v 0 10 20 30 40 50 60 70 tcv os (v/c) number of amplifiers 10238-008 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 v sy = 15 v , 5v soic, a grade 0 20 40 60 80 100 120 140 tcv os (v/c) number of amplifiers 10238-308 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 v sy = 15 v , 5v soic, b grade 0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 i sy (ma) v sy (v) + 25 c ? 40 c + 85 c + 125 c 10238-218 v o = 0v
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 13 of 25 figure 23 . output voltage swing vs. temperature , v sy = 5 v figure 24 . input bias current , v sy = 5 v figure 25 . input bias current (i b ) vs. temperature , v sy = 5 v figure 26 . output voltage swing vs. temperature, v sy = 1 5 v figure 27 . input bias current , v sy = 15 v figure 28 . input bias current (i b ) vs. temperature , v sy = 15 v 3.75 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 ?50 ?25 0 25 50 75 100 125 output vo lt age swing (v) temper a ture (c) v oh = 1ma v ol = 1ma 10238-423 v s = 5v 350 0 number of amplifiers input bias current (na) 10238-013 50 100 150 200 250 300 ?1.0 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 more v sy = 5v ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 i b (na) ?0.2 ?0.1 0 ?50 0 50 100 ?25 temper a ture (c) 25 75 125 + i b ?i b 10238-014 v sy = 5v temper a ture (c) 13.75 13.80 13.85 13.90 13.95 14.00 14.05 14.10 14.15 ?50 ?25 0 25 50 75 100 125 output vo lt age swing (v) 10238-426 v s = 15v v oh = 1ma v ol = 1ma 400 0 number of amplifiers input bias current (na) 10238-016 50 100 150 200 250 300 350 ?1 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 more v sy = 15v ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 i b (na) ?0.2 ?0.1 0 ?50 0 50 100 ?25 temper a ture (c) 25 75 125 + i b ? i b 10238-017 v sy = 15v
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 14 of 25 figure 29 . output saturation voltage vs. i load , s ink current , v sy = 5 v figure 30 . output saturation voltage vs. i load , s ource current , v sy = 5 v figure 31 . open - loop gain and phase vs. frequency , v sy = 5 v figure 32 . output saturation voltage vs. i load , sink current, v sy = 1 5 v figure 33 . output dropout voltage vs. i load , s ource curren t, v sy = 15 v figure 34 . open - loop gain and phase vs. frequency, v sy = 15 v 100 1k 10k 0.001 0.01 0.1 1 10 100 output dropout vo lt age (mv) i load (ma) i sink = ?4 0 c i sink = +2 5 c i sink = +8 5 c i sink = +12 5 c 10238-429 v s = 5v C40c t +12 5 c 100 1k 10k 0.001 0.01 0.1 1 10 100 output dropout vo lt age (mv) i load (ma) i source = ?4 0 c i source = +2 5 c i source = +8 5 c i source = +12 5 c 10238-430 v s = 5v C40c t +12 5 c ?150 ?100 ?50 0 50 100 150 ?150 ?100 ?50 0 50 100 150 10k 100k 1m 10m 100m phase margin (degrees) gain (db) frequenc y (hz) gain with c l = 0 p f gain with c l = 10 0 p f gain with c l = 20 0 p f phase with c l = 0 p f phase with c l = 100 p f phase with c l = 20 0 p f 10238-227 v sy = 5v a v = ?1 r l = 2k? 100 1k 10k 100k 0.001 0.01 0.1 1 10 100 output dropout vo lt age (mv) i load (ma) i sink = ?4 0 c i sink = +2 5 c i sink = +8 5 c i sink = +12 5 c 10238-432 v s = 15v C40c t +12 5 c 100 1k 10k 100k 0.001 0.01 0.1 1 10 100 output dropout vo lt age (mv) i load (ma) i source = ?4 0 c i source = +2 5 c i source = +8 5 c i source = +12 5 c 10238-433 v s = 15v C40c t +12 5 c ?150 ?100 ?50 0 50 100 150 ?150 ?100 ?50 0 50 100 150 10k 100k 1m 10m 100m phase margin (degrees) gain (db) frequenc y (hz) 10238-230 v sy = 15v a v = ?1 r l = 2k? gain with c l = 0 p f gain with c l = 10 0 p f gain with c l = 20 0 p f phase with c l = 0 p f phase with c l = 100 p f phase with c l = 20 0 p f
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 15 of 25 figure 35 . psrr vs. temperature , v sy = 5 v to 15 v figure 36 . psrr vs. frequency, v sy = 5 v figure 37 . cmrr vs. temperature , v sy = 5 v figure 38 . cmrr vs. frequency , v sy = 5 v and v sy = 15 v figure 39 . psrr vs. frequency , v sy = 15 v figure 40 . cmrr vs. temperature , v sy = 15 v 124 125 126 127 128 129 130 131 132 133 ?50 0 50 100 ?25 25 psrr (db) temper a ture (c) 75 125 10238-035 v sy = 5v t o 15v ?20 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) psrr? psrr+ v sy = 5v 10238-034 141 142 143 144 145 146 147 148 149 150 151 152 ?50 0 50 ?25 25 temper a ture (c) cmrr (db) 75 100 125 10238-030 v sy = 5v cmrr (db) 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m 10m frequenc y (hz) v sy = 15v v sy = 5v 10238-029 ?20 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) psrr? psrr+ v sy = 15v 10238-037 153 154 155 156 157 158 159 ?50 0 50 ?25 25 temper a ture (c) cmrr (db) 75 100 125 10238-033 v sy = 15v
ADA4077-1/ada4077-2/ada4077-4 data sheet rev. d | page 16 of 25 figure 41. closed-loop gain vs. frequency, v sy = 5 v figure 42. output impedance (z out ) vs. frequency, v sy = 5 v figure 43. large signal transient response, v sy = 5 v figure 44. closed-loop gain vs. frequency, v sy = 15 v figure 45. output impedance (z out ) vs. frequency, v sy = 15 v figure 46. large signal transient response, v sy = 15 v 50 ?50 1k 10k 100k 100m 10m 1m closed-loop gain (db) frequency (hz) ?40 ?30 ?20 ?10 0 10 20 30 40 g = 1 g = 10 g = 100 10238-028 v sy = 5v 0.001 0.01 0.1 1 10 100 1k 100 1k 10k 100k 1m 10m z out ( ? ) frequency (hz) a v = +100 v sy = 5v a v = +10 a v = +1 10238-036 time (100s/div) 0v voltage (0.2v/div) v sy = 5v v in = 1v p-p a v = +1 r l = 2k ? c l = 300pf 10238-040 50 ?50 1k 10k 100k 100m 10m 1m closed-loop gain (db) frequency (hz) ?40 ?30 ?20 ?10 0 10 20 30 40 g = 1 g = 10 g = 100 10238-031 v sy = 15v 0.001 0.01 0.1 1 10 100 1k 100 1k 10k 100k 1m 10m z out ( ? ) frequency (hz) a v = +100 v sy = 15v a v = +10 a v = +1 10238-039 time (100s/div) vol t age (1v/div) v sy = 15v v in = 4v p-p a v = +1 r l = 2k ? c l = 300pf 10238-043 0v
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 17 of 25 figure 47 . small signal transient response , v sy = 5 v figure 48 . positive overload recovery , v sy = 5 v figure 49 . negative overload recovery , v sy = 5 v figure 50 . small signal transient response , v sy = 15 v figure 51 . positive overload recovery , v sy = 15 v figure 52 . negative overload recovery , v sy = 15 v ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 volt age (v) time (ms) 10238-344 v sy = 5v v in = 100mv p-p a v = +1 load = 2k?||1000pf time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?1 1 3 5 output vo lt age (v) v sy = 5v a v = ?100 v in = 200mv r l = 10k? input output 10238-046 time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?5 ?3 ?1 1 output vo lt age (v) v sy = 5v a v = ?100 v in = 200mv r l = 10k? input output 10238-047 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 volt age (v) time (ms) 10238-247 v sy = 15v v in = 100mv p-p a v = +1 load = 2k? || 1000pf ?5 0 5 10 15 20 25 30 35 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 ?10 0 10 20 30 40 50 60 70 90 80 output (v) input (v) time (s) v sy = 15v v in = 200mv p-p a v = ?100 load = 10k? 10238-248 time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?15 ?10 ?5 0 output vo lt age (v) v sy = 15v a v = ?100 v in = 200mv r l = 10k? input output 10238-051
ADA4077-1/ada4077-2/ada4077-4 data sheet rev. d | page 18 of 25 figure 53. small signal overshoot vs. load capacitance, v sy = 5 v figure 54. positive 0.1% settling time, v sy = 5 v figure 55. negative 0.1% settling time, v sy = 5 v figure 56. small signal overshoot vs. load capacitance, v sy = 15 v figure 57. positive 0.1% settling time, v sy = 15 v figure 58. negative 0.1% settling time, v sy = 15 v 0 5 10 15 20 25 30 35 40 1p 10p 100p 1n 10n overshoot (%) load capacitance (f) os+ os? v sy = 5v r l = 2k ? 10238-250 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 output (v) input (v) time (1s/div) v sy = 5v v in = 1v p-p r l = 2k ? 10238-251 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 output (v) input (v) 10238-252 v sy = 5v v in = 1v p-p r l = 2k ? time (1s/div) 0 5 10 15 20 25 30 35 40 1p 10p 100p 1n 10n overshoot (%) load capacitance (f) os+ os? v sy = 15v r l = 2k ? 10238-253 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 output (v) input (v) v sy = 15v v in = 10v p-p r l = 2k ? 10238-254 time (1s/div) ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 output (v) input (v) v sy = 15v v in = 10v p-p r l = 2k ? 10238-255 time (1s/div)
data sheet ADA4077-1/ada4077-2/ada4077-4 rev. d | page 19 of 25 figure 59. voltage noise density vs. frequency, v sy = 5 v and v sy = 15 v figure 60. thd + n vs. frequency, v sy = 5 v figure 61. 0.1 hz to 10 hz noise, v sy = 5 v figure 62. voltage noise corner vs. frequency, v sy = 15 v and v sy = 5 v figure 63. thd + n vs. frequency, v sy = 15 v figure 64. 0.1 hz to 10 hz noise, v sy = 15 v 1k 100 10 1 10 10m 1m 100k 10k 1k 100 voltage noise density (nv/ hz) frequency (hz) v sy = 15v v sy = 5v a v = +1 10238-053 10238-155 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k thd + noise (%) frequency (hz) bandwidth = 80khz bandwidth = 500khz v sy = 5v time (1s/div) input vol t age (50nv/div) v sy = 5v 10238-054 100 0 03.0 voltage noise corner (nv/ hz) frequency (hz) 10238-153 10 20 30 40 50 60 70 80 90 0.5 1.0 1.5 2.0 2.5 v sy = 5v v sy = 15v 10238-158 10 100 1k 10k 100k thd + noise (%) frequency (hz) bandwidth = 80khz bandwidth = 500khz 0.0001 0.001 0.01 0.1 1 10 100 v sy = 15v time (1s/div) input vol t age (50nv/div) v sy = 15v 10238-058
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 20 of 25 figure 65 . input bias current (i b ) vs. common - mode voltage (v cm ) figure 66 . channel separation , v sy = 15 v figure 67 . current noise density , v s y = 15 v figure 68 . current noise density , v s y = 5 v ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 ?20 ? 15 ?10 ? 5 0 5 10 15 20 i b (pa) v cm (v) m e a n m e a n +3 m e a n C3 v sy = 15v C15v v cm +15v t a = 25c 10238-219 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 100 100k 10k 1k 1m channel separation (db) frequency (hz) 10238-244 v sy = 15v v in = 10v p-p a v = +1 r l = 10k? 2k ? + v in ch a v cc v ee ? + 2k 10k 1k ch b, ch c, ch d v cc v ee 0.1 1 10 100 1 10 100 1k 10k 100k current noise densit y (pa/hz) frequenc y (hz) v sy = 15v 10238-267 0.1 1 10 100 1 10 100 1k 10k 100k current noise densit y (pa/hz) frequenc y (hz) v sy = 5v 10238-268
data sheet ada4077- 1 /ada4077- 2/ada4077 - 4 rev. d | page 21 of 25 theory of operation the ada4077 - 1 , ada4077 - 2 , and ada4077 - 4 are the sixth generation of the analog devices, inc., industry - standard op07 amplifier family. the ada4077 - 1 , ada4077 - 2 , and ada4077 - 4 are high precision, low noise operational amplifier s with a combination o f extremely low offset voltage and very low input bias currents. unlike jfet amplifiers, the low bias and offset currents are relatively insensitive to ambient temperatures, even up to 125c. the analog devices proprietary process technology and linear des ign expertise have produced a high voltage amplifier with superior performance to the op07 , op77 , op177 , and op1177 in tiny , 8 - lead soic and 8 - lead msop package s ( ada4077 - 1 and ada4077 - 2 ) and 14 - lead tssop and 14 - lead soic packages ( ada4077 - 4 ) . despite their small size, the ada4077 - 1 , ada4077 - 2 , and ada4077 - 4 offer numerous improvements, including low wideband noise, wide bandwidth , lower offset and offset drift, lower input bias current, and complet e freedom from phase inversion. the ada4077 - 1 , ada4077 - 2 , and ada4077 - 4 ha ve a specified operating temperature range of ? 40 c to +125 c with a n m sl1 rat ing , which is as wide as any similar device in a plastic surface - mount package . this msl1 rating is increasingly important as printed circuit board ( pcb ) and overall system sizes continue to shrink, causing internal system tempe ratures to rise. in the ada4077 - 1 , ada4077 - 2 , and the ada4077 - 4 , the p ower consumption is reduced by a factor of four compared to the op177 , and the bandwidth and slew rate are both increase d by a factor of six. the low power dissipation and very stable performance vs. temperature also reduce warmup drift errors to insignificant levels. inputs are protected internally from overvoltage conditions referenced to either supply rail. like any high performance amplifier, maximum performance is achieved by following appropri ate circuit and pcb guidelines.
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 22 of 25 application s information output phase reversa l phase reversal is defined as a change o f polarity in the amplifier transfer function. many operational amplifiers exhibit phase reversal when the voltage a pplied to the input is greater than the maximum common - mode voltage . in some instances, this phase reversal can cause permanent damage to th e amplifier. in feedback loops, it can result in system lockups or equipmen t damage . the ada4077 - 1 , ada4077 - 2 , and the ada4077 - 4 are immune to phase reversal problems even at input voltages beyond t he power supply settings . figure 69 . no phase reversal low power linearized rtd a common application for a single element varying bridge is a resistance temperature detector ( rtd ) ther mometer amplifier, as shown in figure 70 . the excitation is delivered to the bridge by a 2.5 v reference ap plied at the top of the bridge. rtds can have a thermal resistance as high as 0.5c to 0.8c per mw. to minimize errors due to resistor drift, keep the current low through each leg of the bridg e . in this circuit, the amplifier supply current flows through the bridge. however, at a maximum supply current of 500 a for the ada4077 - 2 , the rtd dissipates less than 0.1 mw of power, even at the highest resistance. therefore, e rrors due to power dissipation in t he bridge are kept under 0.1c. calibration of the bridge is made at the minimum value of the temperature to be measured by adjusting r p until the output is zero. to calibrate the output span, set the full - scale and linearity potentiometers to midpoint , and apply a 500c temperature to the sensor , or substitute the e quivalent 500c rtd resistance. adjust the full - scale potentiometer for a 5 v output. finally, apply 250c or the equivalent rtd resistance , and adjust the linearity potentiometer for 2.5 v output. the circuit achieves higher than 0.5c accuracy after adjustment. figure 70 . low power linearized rtd circuit proper board layout the ada4077 - 1 , ada4077 - 2 , and ada4077 - 4 are high precision device s . to ensure optimum performance at the pcb leve l, care must be taken in the design of the board layout. to avoid leakage currents, maintain a clean and moisture free board surface. coating the surface creates a barrier to moisture accumulation , and reduce s parasitic resistance on the board. keeping sup ply traces short and p roperly bypassing the power supplies minimizes the power supply disturbances caused by the output current variation, such as when driving an ac signal into a heavy load. connect b ypass capacitors as closely as possible to the device supply pins. stray capacitances are a concern at the outputs and the inputs of the amplifier. it is recommended that the signal traces be kept at least 5 mm from supply lines to minimize coup ling. a variation in temperature across the pcb can cause a mis match in the seebeck voltages at solder join ts and other points where dissi milar metals are in contact, resulting in thermal voltage errors. to minimize these thermocouple effects, orient resistors so that heat sources warm both ends equally. ensure, where possible, that i nput signal paths contain matching numbers and types of components, to match the number and type of thermocouple junctions. for example, dummy components such as zero value resistors can be used to match real resistors in the opposite inpu t path. place m atching components in close proximity to each other , and orient them in the same manner. ensure that leads are of equal length so that thermal conduction is in equilibrium. keep heat sources on the pcb as far away from amplifier input circui try as is practical. the u se of a ground plane is highly recommended . a ground plane reduces emi noise and maintain s a constant temperature across the circuit board . 2 ch1 5.00v ch2 5.00v m10.0ms a ch1 300mv 1 t 0.000% 10238-063 200? 500? full-scale adj 4.37k? 100? 100? 20? r p , zero adj 4.12k? 4.12k? 5k? linearity adj 49.9k? adr4525 +15v 0.1f v+ 100? rtd 1/2 ada4077-2 7 6 5 1/2 ada4077-2 1 8 2 3 4 v? v out 0.1f 10238-064
data sheet ADA4077-1/ada4077-2/ada4077-4 rev. d | page 23 of 25 outline dimensions figure 71. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters figure 72. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10
ada4077- 1 /ada4077- 2/ada4077 - 4 data sheet rev. d | page 24 of 25 figure 73 . 14 - lead thin shrink small outline package [tssop] (ru - 14) dimensions shown in millimeters figure 74 . 14 - lead standard small outline package [soic_n] narrow body (r - 14) dimensions shown in millimeters and (inches) compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 sea ting plane controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc se a ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45
data sheet ADA4077-1/ada4077-2/ada4077-4 rev. d | page 25 of 25 ordering guide model 1 temperature range package description package option branding ADA4077-1armz ?40c to +125c 8-lead mini small outline package [msop] rm-8 a35 ADA4077-1armz-r7 ?40c to +125c 8-lead mi ni small outline package [msop] rm-8 a35 ADA4077-1armz-rl ?40c to +125c 8-lead mi ni small outline package [msop] rm-8 a35 ADA4077-1arz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ADA4077-1arz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ADA4077-1arz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ADA4077-1brz ?40c to +125c 8-lead standa rd small outline package [soic_n] r-8 ADA4077-1brz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ADA4077-1brz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4077-2armz ?40c to +125c 8-lead mini small outline package [msop] rm-8 a2x ada4077-2armz-r7 ?40c to +125c 8-lead mi ni small outline package [msop] rm-8 a2x ada4077-2armz-rl ?40c to +125c 8-lead mi ni small outline package [msop] rm-8 a2x ada4077-2arz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4077-2arz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4077-2arz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4077-2brz ?40c to +125c 8-lead standa rd small outline package [soic_n] r-8 ada4077-2brz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4077-2brz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4077-4aruz ?40c to +125c 14-lead thin sh rink small outline package [tssop] ru-14 ada4077-4aruz-r7 ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ada4077-4aruz-rl ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ada4077-4arz ?40c to +125c 14-lead standard small outline package [soic_n] r-14 ada4077-4arz-r7 ?40c to +125c 14-lead standard small outline package [soic_n] r-14 ada4077-4arz-rl ?40c to +125c 14-lead standard small outline package [soic_n] r-14 1 z = rohs compliant part. ?2012C2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10238-0-10/16(d) www.analog.com/ADA4077-1/ada4077-2/ada4077-4

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